1. Field of the Invention
This invention relates to digital pulse width modulated (PWM) display systems, more particularly to those digital PWM systems that receive display data with varying frame rates and that store PWM sequences in memory for each frame rate.
2. Background of the Invention
Digital PWM systems typically display data in the format of one sample of data per picture element (pixel) on the final image. The PWM scheme is dependent upon how many bits per pixel are generated for the given image. For example, a 4-bit system would display the most significant bit (MSB) for 8/15 the frame time, the next MSB for 4/15 the frame time, the next to least significant bit (LSB) for 2/15 the frame time, and the LSB for 1/15 the frame time. It should be noted that the LSB time is equal to 1 divided by 2'-1 where i is the number of bits per sample. This is referred to as the LSB time, and the higher order bit times are typically discussed as multiples of this LSB time, with the MSB have 8 LSB times, etc. The exact order and duration of PWM bits is called a PWM sequence.
As can be seen from the above discussion, the LSB time is tightly coupled with the frame time, as it depends upon the frame time for determining its length. In order for a display system to handle a range of frame rates, several PWM sequences must be stored and interpreted in real time to initiate data transfer to the display system with the correct timing. PWM sequences could be used that were not adapted for the varying frame rates. However, more tightly coupled sequences are more efficient because more of the available time can be used for light output.
The storing of several of these sequences in memory increases the need for memory and thereby increases the cost for the system. Therefore, a method is needed that allows for tight coupling between the PWM sequence and the frame rate, yet does not require large amounts of memory.